JETSON ORIN BASEBOARD: HOW MUCH VOLTAGE REACHES THE MODULE A plain-text summary of the pdnsim DC voltage-drop report at https://demo.simulibrium.com/jetson-orin-baseboard/ Computed, not measured. Every result here was computed by pdnsim, Simulibrium's DC voltage-drop tool, from the board's published KiCad file. NVIDIA's limits and the part values are quoted from the cited sources, and numbers marked "our arithmetic, not run" are not runs. pdnsim's measured accuracy is none yet. There is no verdict: the copper thickness is not confirmed, and judging is off (judge: false); see WHY THERE IS NO VERDICT. This file is generated from the page's data files by tools/jetson_report.py in the simulibrium-demo repository. Its numbers are the data's values, rounded as the page rounds them; nothing here was computed anew. A few numbers are marked "our arithmetic, not run": they are worked out by hand from pdnsim's results, as on the page. Page: https://demo.simulibrium.com/jetson-orin-baseboard/ Data: https://demo.simulibrium.com/jetson-orin-baseboard/data/manifest.json (every run, NVIDIA's limits, the sources) https://demo.simulibrium.com/jetson-orin-baseboard/data/scenario_nx40w.json (scenario E) https://demo.simulibrium.com/jetson-orin-baseboard/data/scenario_nx25.json (scenario A) https://demo.simulibrium.com/jetson-orin-baseboard/data/scenario_nano15.json (scenario B) https://demo.simulibrium.com/jetson-orin-baseboard/data/scenario_nano25cp.json (scenario G) The copper images (data/*.webp) and their encoding are described in manifest.json, raster.note. THE BOARD AND THE QUESTION ========================== Board: Jetson Orin Baseboard by Antmicro, revision 1.3.4, file jetson-orin-baseboard.kicad_pcb at commit 34f0e7f5fbca441191e20ed55d93cf8614e12bed (SHA-256 eaeb87f5bceb46097c8161cf5e990c3609bf667f5a53668f76aa93595bd636ca), analysed unmodified. Copyright (c) 2022-2026 Antmicro, licensed Apache-2.0. Source: https://github.com/antmicro/jetson-orin-baseboard/tree/34f0e7f5fbca441191e20ed55d93cf8614e12bed This is Antmicro's open-source carrier board for NVIDIA's Jetson Orin NX and Orin Nano modules. The module plugs into the board's SO-DIMM socket, J15. It takes its power through its VDD_IN pins. The board has eight copper layers. The question: NVIDIA sets a minimum voltage at the module's VDD_IN pins. Between the board's input and those pins, some voltage is lost: in the copper, and in the parts the current flows through. How much is left at the pins? How close is that to NVIDIA's minimum? The board feeds the module in one of two ways. An Orin NX leaves its MODULE_ID pin floating. That turns on the eFuse U48, which feeds VDD_IN from the board's 9 to 20 V input through two P-FETs, Q15 and Q18. A 5 V-only module ties MODULE_ID to GND. It is fed from the carrier's 5 V buck through the eFuse U29. An NVIDIA forum moderator names the Orin Nano as a 5 V-only module; that is a forum post, not a data sheet. IN SHORT ======== - Scenario E. Orin NX 16GB at a constant 40 W in MAXN_SUPER mode, from a 9.0 V input. The module sees 8.078 V. That is 78 mV above 8.00 V, the minimum NVIDIA requires in this mode. The carrier takes 922 mV of the 1000 mV between 9.0 V and 8.0 V: 643 mV in Q15 and Q18, 223 mV in U48 at TI's 45 mΩ maximum, 2 mV in the jumper R287 and 54 mV in copper. This margin is not a bound. - Scenario A. Orin NX 16GB at its 25 W mode budget, from the same 9.0 V input. The module sees 8.418 V, 3.67 V above NVIDIA's 4.75 V minimum. No narrow margin there. - Scenario B. Orin Nano 8GB at its 15 W mode budget, fed from the carrier's 5 V buck. The carrier takes 148 mV, and the module sees 4.852 V, 102 mV above 4.75 V. - Scenario G. Orin Nano 8GB at a constant 25 W, its 25 W* super-mode budget, fed from the 5 V buck. The module sees 4.742 V: 8 mV below 4.75 V, NVIDIA's minimum for VDD_IN. The carrier takes 258 mV: 237 mV in U29 at TI's 45 mΩ maximum over temperature, 6 mV in the jumpers R172 and R287 and 15 mV in copper. G is a bound case, not an operating point. Keep three things in mind: 1. Computed, not measured. pdnsim's measured accuracy is none yet. 2. No verdict. pdnsim gives no pass or fail. The copper thickness is not confirmed: the board file gives every copper layer KiCad's default 35 µm, and we have no fab stackup. Thinner copper would make the copper's drops larger. We also turned judging off (judge: false). 3. Bounds. A bound case takes the inputs we name at their worst. A margin is a bound only if every input is at its worst, so neither E's nor G's margin is a bound. - E's margin is not a bound. The two P-FETs, Q15 and Q18, are taken at Toshiba's maximum resistance at 25 °C. Each carries 6.43 A: above its 6.0 A DC rating and, by I²R, beyond its 1 W power rating (our arithmetic, not run). Q18's gate is driven to only about 4.3 V at the 9 V input, below the 4.5 V at which Toshiba gives that maximum. So they would heat and their resistance would rise: the true margin is almost certainly smaller, and possibly negative. Each 10 % more on both costs about 64 mV at E's current; at a constant 40 W, about 11 % more uses the whole margin (our arithmetic, not run). See WHY E'S MARGIN IS NOT A BOUND. - G is a bound case. It takes the 25 W* budget as a constant 25 W, and the eFuse U29 at TI's maximum resistance over −40 to 125 °C. Things not modelled can still take more of the margin: the connector and socket contacts, the 5 V buck's setpoint tolerance, the copper's real thickness. The module type comes from a forum statement. So G is not a finding that the board fails Super mode. At TI's typical 28.2 mΩ (at VIN 12 V, IOUT 3 A, TJ 25 °C; a little higher at 5 V in TI's Figure 6-2, and TI gives no typical value for a hot part) U29 would take about 149 mV, and the module would see about 4.830 V, 80 mV above 4.75 V (our arithmetic at G's current, not run). See SCENARIO G AND U29'S CURRENT LIMIT. - The one sourced bound on the module's current that we read is NVIDIA's 5 A absolute maximum for VDD_IN (scenario D, numbers only): 70 mV above 8.00 V, with the same part values as E. D's margin is not a bound either, for the same reason as E's. THE MARGIN AT THE MODULE'S PINS: EVERY RUN ========================================== This lists all seven runs, A to G. Four have a 3D view on the page: E, A, B and G. C, D and F are numbers only: runs C and D were used to find E's current, and run F to find G's. D is also NVIDIA's 5 A absolute maximum. Each run is one DC solution at a constant module current. Carrier's drop is the voltage lost on the carrier, from where the supply enters the copper to the module's VDD_IN pins and back on GND. VDD_IN at the module is pdnsim's computed voltage between the SO-DIMM's VDD_IN pins and its GND pins. The parts' resistances are stated values: TI's maximum over temperature for the eFuses, ROHM's maximum for the jumpers, and Toshiba's maximum at 25 °C for the P-FETs, which is not a bound. The module's power is our arithmetic: its current times its computed VDD_IN. It is an input power, not a loss. Scenario E: Orin NX 16GB, MAXN_SUPER budget at a constant 40 W, 9.0 V input --------------------------------------------------------------------------- - 3D view on the page: yes - Supply: 9.0 V at J12 pad 1 - Module current: 4.952 A (current basis: average), 40.00 W at its computed VDD_IN - Carrier's drop: 922.28 mV: 868.10 mV in parts, 54.19 mV in copper - VDD_IN at the module: 8.0777 V - Against NVIDIA's limit: 78 mV above 8.00 V (MAXN_SUPER minimum) - pdnsim's status line: NO VERDICT, 0 exclusions, 3 not judged - Basis of the module current, as we entered it: the mode's name in NVIDIA's data sheet, read as its power budget, not a stated draw (NVIDIA's r36.4 guide calls MAXN "an unconstrained power mode" in which "hardware throttling is engaged when the total module power exceeds the TDP budget"; no MAXN_SUPER limit table was read; the sourced bound on the module's current is scenario D, NVIDIA's 5 A absolute maximum): "Jetson Orin NX 16GB Modes: 10W | 15W | 25W | 40W (MAXN_SUPER)" (DS-10712-001_v1.7 (Feb 2026), printed p. 3. A constant 40 W at the module's own VDD_IN: I × V_module(I) = 40 W solved on runs C and D (V_module linear in I), 4.9519 A at 8.0777 V, entered as 4.952 A. Table 5-1 note (p. 44): MAXN_SUPER needs 8.0 V minimum) Scenario A: Orin NX 16GB, 25 W mode budget, 9.0 V input ------------------------------------------------------- - 3D view on the page: yes - Supply: 9.0 V at J12 pad 1 - Module current: 2.780 A (current basis: average), 23.4 W at its computed VDD_IN - Carrier's drop: 582.24 mV: 548.01 mV in parts, 34.23 mV in copper - VDD_IN at the module: 8.4178 V - Against NVIDIA's limit: 3668 mV above 4.75 V (minimum) - Against NVIDIA's limit: about 3918 mV above 4.50 V (approx., throttling) - pdnsim's status line: NO VERDICT, 0 exclusions, 3 not judged - Basis of the module current, as we entered it: the mode's power budget, NVIDIA's average-power throttling limit for VDD_IN: an upper bound on the module's average, not a stated draw, used here as a constant current: "Jetson Orin NX 16GB | 25W | VDD_IN Average Power: 25W | OC2 | CPU: 50% GPU: 50% | VDD_IN Instantaneous Power: 30W" (Jetson Linux Developer Guide r36.4, 'Software-Based Power Consumption Modeling', Orin NX/Nano table (cells joined with |). 25 W / 9.0 V = 2.78 A) Scenario B: 5 V-only module (Orin Nano 8GB), 15 W mode budget, from the 5 V buck -------------------------------------------------------------------------------- - 3D view on the page: yes - Supply: 5.0 V at L4 pad 2 - Module current: 3.000 A (current basis: average), 14.6 W at its computed VDD_IN - Carrier's drop: 147.81 mV: 138.45 mV in parts, 9.36 mV in copper - VDD_IN at the module: 4.8522 V - Against NVIDIA's limit: 102 mV above 4.75 V (minimum) - Against NVIDIA's limit: about 352 mV above 4.50 V (approx., throttling) - pdnsim's status line: NO VERDICT, 0 exclusions, 3 not judged - Basis of the module current, as we entered it: the mode's power budget, NVIDIA's average-power throttling limit for VDD_IN: an upper bound on the module's average, not a stated draw, used here as a constant current: "Jetson Orin Nano 8GB | 15W | VDD_IN Average Power: 15W | OC2 | CPU: 50% GPU: 50% | VDD_IN Instantaneous Power: 20W" (Jetson Linux Developer Guide r36.4, 'Software-Based Power Consumption Modeling', Orin NX/Nano table (cells joined with |). 15 W / 5.0 V = 3.0 A) Scenario G: Orin Nano 8GB, 25 W* super-mode budget at a constant 25 W, from the 5 V buck (a 5 V-only module) ------------------------------------------------------------------------------------------------------------ - 3D view on the page: yes - Supply: 5.0 V at L4 pad 2 - Module current: 5.2726 A (current basis: average), 25.00 W at its computed VDD_IN - Carrier's drop: 258.40 mV: 242.99 mV in parts, 15.41 mV in copper - VDD_IN at the module: 4.7416 V - Against NVIDIA's limit: 8 mV below 4.75 V (minimum) - Against NVIDIA's limit: about 242 mV above 4.50 V (approx., throttling) - pdnsim's status line: NO VERDICT, 0 exclusions, 3 not judged - Basis of the module current, as we entered it: the mode's power budget, NVIDIA's average-power throttling limit for VDD_IN: an upper bound on the module's average, not a stated draw, used here as a constant current: "25W* | VDD_IN Average Power: 25W | OC2 | CPU: 50% GPU: 50% | VDD_IN Instantaneous Power: 25W" (Jetson Linux Developer Guide r36.4, 'Software-Based Power Consumption Modeling', the Orin Nano 8GB rows (cells joined with |), and its footnote: '* The 25W module TDP budget for Jetson Orin Nano 8GB is applicable only with jetson-orin-nano-devkit-super flash configurations.'. A constant 25 W at the module: I × V(I) = 25 W on run F (5.0 A) with V = 5.0 V - R_eff × I, R_eff = 245.1335 mV / 5.0 A = 49.0267 mΩ: 5.27259 A at 4.74150 V (our arithmetic), entered as 5.2726 A; a constant current in the run) Scenario C: Orin NX 16GB, MAXN_SUPER at 4.44 A (40 W at the 9.0 V input), 9.0 V input ------------------------------------------------------------------------------------- - 3D view on the page: no (numbers only) - Supply: 9.0 V at J12 pad 1 - Module current: 4.440 A (current basis: average), 36.2 W at its computed VDD_IN - Carrier's drop: 842.10 mV: 792.62 mV in parts, 49.48 mV in copper - VDD_IN at the module: 8.1579 V - Against NVIDIA's limit: 158 mV above 8.00 V (MAXN_SUPER minimum) - pdnsim's status line: NO VERDICT, 0 exclusions, 3 not judged - Basis of the module current, as we entered it: the mode's name in NVIDIA's data sheet, read as its power budget, not a stated draw (NVIDIA's r36.4 guide calls MAXN "an unconstrained power mode" in which "hardware throttling is engaged when the total module power exceeds the TDP budget"; no MAXN_SUPER limit table was read; the sourced bound on the module's current is scenario D, NVIDIA's 5 A absolute maximum): "Jetson Orin NX 16GB Modes: 10W | 15W | 25W | 40W (MAXN_SUPER)" (DS-10712-001_v1.7 (February 2026), printed page 3 (PDF page 9). 40 W / 9.0 V = 4.44 A. Same data sheet, Table 5-1 note (printed p. 44): 'MAXN_SUPER at 40W for Jetson Orin NX requires minimum 8.0V to the VDD_IN.') Scenario D: Orin NX 16GB, MAXN_SUPER bound: 5.0 A, 9.0 V input -------------------------------------------------------------- - 3D view on the page: no (numbers only) - Supply: 9.0 V at J12 pad 1 - Module current: 5.000 A (current basis: peak), 40.4 W at its computed VDD_IN - Carrier's drop: 929.80 mV: 875.17 mV in parts, 54.63 mV in copper - VDD_IN at the module: 8.0702 V - Against NVIDIA's limit: 70 mV above 8.00 V (MAXN_SUPER minimum) - pdnsim's status line: NO VERDICT, 0 exclusions, 3 not judged - Basis of the module current, as we entered it: NVIDIA's VDD_IN absolute-maximum current, data sheet Table 5-2, printed page 45: "IDDMAX VDD_IN Imax - 5 A" (also 40 W at 8.0 V); an absolute maximum, not an operating point Scenario F: Orin Nano 8GB, 25 W* super-mode budget at 5.0 A (25 W at the 5.0 V setpoint), from the 5 V buck ----------------------------------------------------------------------------------------------------------- - 3D view on the page: no (numbers only) - Supply: 5.0 V at L4 pad 2 - Module current: 5.000 A (current basis: average), 23.8 W at its computed VDD_IN - Carrier's drop: 245.13 mV: 230.45 mV in parts, 14.68 mV in copper - VDD_IN at the module: 4.7549 V - Against NVIDIA's limit: 5 mV above 4.75 V (minimum) - Against NVIDIA's limit: about 255 mV above 4.50 V (approx., throttling) - pdnsim's status line: NO VERDICT, 0 exclusions, 3 not judged - Basis of the module current, as we entered it: the mode's power budget, NVIDIA's average-power throttling limit for VDD_IN: an upper bound on the module's average, not a stated draw, used here as a constant current: "25W* | VDD_IN Average Power: 25W | OC2 | CPU: 50% GPU: 50% | VDD_IN Instantaneous Power: 25W" (Jetson Linux Developer Guide r36.4, 'Software-Based Power Consumption Modeling', the Orin Nano 8GB rows (cells joined with |), and its footnote: '* The 25W module TDP budget for Jetson Orin Nano 8GB is applicable only with jetson-orin-nano-devkit-super flash configurations.' 25 W / 5.0 V = 5.0 A) NVIDIA'S LIMITS AND THEIR SOURCES ================================= - 8.00 V: NVIDIA's minimum VDD_IN for an Orin NX in MAXN_SUPER at 40 W. NVIDIA, Jetson Orin NX Series Modules Data Sheet, DS-10712-001_v1.7 (February 2026), note under Table 5-1, printed page 44: "MAXN_SUPER at 40W for Jetson Orin NX requires minimum 8.0V to the VDD_IN." (https://developer.nvidia.com/downloads/jetson-orin-nx-module-series-data-sheet) - 4.75 V: NVIDIA's minimum VDD_IN for a module whose MODULE_ID is high (an Orin NX). NVIDIA, Jetson Orin NX Series Modules Data Sheet, DS-10712-001_v1.7 (February 2026), Table 5-1, printed page 44: "VDD_IN (MODULE_ID high) 4.75 - 20 V" (https://developer.nvidia.com/downloads/jetson-orin-nx-module-series-data-sheet) - 4.50 V: NVIDIA's under-voltage throttling point for the Orin NX 16GB (its OC1 event, CPU and GPU throttled). NVIDIA, Jetson Linux Developer Guide r36.4, Platform Power and Performance, "Software-Based Power Consumption Modeling", the Orin NX 16GB 25W row (NVIDIA's software guide; the design guide DG-10931-001 was not read): "Under Voltage: approx. 4.5V | OC1 | CPU: 87.5% GPU: 87.5%" (https://docs.nvidia.com/jetson/archives/r36.4/DeveloperGuide/SD/PlatformPowerAndPerformance/JetsonOrinNanoSeriesJetsonOrinNxSeriesAndJetsonAgxOrinSeries.html) - 4.75 V: NVIDIA's minimum VDD_IN for a module whose MODULE_ID is low (a 5 V-only module). NVIDIA, Jetson Orin NX Series Modules Data Sheet, DS-10712-001_v1.7 (February 2026), Table 5-1, printed page 44 (the Orin NX data sheet's row; the Orin Nano's own data sheet could not be downloaded): "VDD_IN (MODULE_ID low) 4.75 5 5.25 V" (https://developer.nvidia.com/downloads/jetson-orin-nx-module-series-data-sheet) - 4.50 V: NVIDIA's under-voltage throttling point for the Orin Nano 8GB (its OC1 event). NVIDIA, Jetson Linux Developer Guide r36.4, Platform Power and Performance, "Software-Based Power Consumption Modeling", the Orin Nano 8GB 15W and 25W* rows, the cells both rows share (the throttling level that follows differs: 87.5 % in the 15W row, 50 % in the 25W* row; NVIDIA's software guide; the design guide DG-10931-001 was not read): "Under Voltage: approx. 4.5V | OC1" (https://docs.nvidia.com/jetson/archives/r36.4/DeveloperGuide/SD/PlatformPowerAndPerformance/JetsonOrinNanoSeriesJetsonOrinNxSeriesAndJetsonAgxOrinSeries.html) HOW EACH SCENARIO'S CURRENT WAS CHOSEN ====================================== E, a constant 40 W. E's 40 W is the mode's name read as a budget, not a bound: NVIDIA calls MAXN an unconstrained mode that throttles at its TDP budget, and we read no MAXN_SUPER limit table. A module drawing a constant 40 W takes the current at which that current times its own VDD_IN is 40 W. Run C (4.44 A, 40 W at the 9.0 V input) gives the module only 36.2 W at its computed 8.158 V. Run D (5.00 A, 40 W at 8.0 V and also NVIDIA's 5 A absolute-maximum VDD_IN current) gives 40.4 W at 8.070 V. Between them the computed VDD_IN is linear in the current, so the 40 W point is at 4.952 A (our arithmetic on C and D). Run E at that current gives 40.00 W at 8.078 V, between D and C. G, a constant 25 W, is found the same way. Run F (5.00 A, 25 W at the 5.0 V setpoint) gives the module only 23.8 W at its computed 4.755 V. Taking F's drop as proportional to the current (245.13 mV / 5.0 A = 49.03 mΩ), the module receives 25 W at 5.2726 A (our arithmetic on F). Run G at that current gives 25.00 W at 4.7416 V. A straight line through B and F gives 4.7416 V at that current (our arithmetic). A, B and F are constant currents: a mode's power over its supply's nominal voltage (9.0 V for A, 5.0 V for B and F). A module that draws constant power would draw a little more as VDD_IN sags: about 7 % in A, 3 % in B and 5 % in F (V_input / V_module − 1; not run). For F that correction was run: it is G, 5.5 % more current than F. The 9.0 V input is our scenario: the low end of Antmicro's recommended range (getting_started.md (https://github.com/antmicro/jetson-orin-baseboard/blob/34f0e7f5fbca441191e20ed55d93cf8614e12bed/doc/source/getting_started.md): "The recommended power supply voltage range for Jetson Orin Baseboard in revision >= 1.3.0 is 9-20 VDC."). At 12 V the module's current would be about a quarter lower (our arithmetic for a constant power, not run). Antmicro's own words on why the module is fed from the input (board_overview.md (https://github.com/antmicro/jetson-orin-baseboard/blob/34f0e7f5fbca441191e20ed55d93cf8614e12bed/doc/source/board_overview.md)): "This enables the use of the Jetson Orin NX in "super" mode which requires a minimum power supply voltage of 8V." That the Orin Nano is a 5 V-only module comes from an NVIDIA forum moderator (forum post (https://forums.developer.nvidia.com/t/how-to-handle-module-id-pin-217/298485), 2024-07-04: "MODULE_ID pin is for power supply option (5V only for Orin nano or 5V ~20V for Orin NX)."; our saved copy's SHA-256 is in the sources), not from a data sheet. Each run's module current and its basis, as we entered it, are under THE MARGIN AT THE MODULE'S PINS: EVERY RUN. WHY E'S MARGIN IS NOT A BOUND ============================= In E the carrier takes 922 mV: 643 mV in Q15 and Q18, 223 mV in U48 at TI's 45 mΩ maximum, 2 mV in the jumper R287 and 54 mV in copper. Q15 and Q18 take 642.8 of E's 922.3 mV. pdnsim takes each at 50 mΩ: Toshiba's data-sheet maximum at 25 °C, ID −4.0 A and |VGS| 4.5 V (typical 42.5 mΩ; data sheet (https://www.farnell.com/datasheets/3622419.pdf)). |VGS| is the gate voltage that turns the part on. Both maxima used here are pulse-test values (the data sheet's Note 4), so they leave out self-heating, and Toshiba states no maximum over temperature. Q18's gate is VCC_IN / 2, from R164 and R165 (4.7 kΩ each): about 4.3 V at a 9 V input. That is below the 4.5 V at which Toshiba gives the 50 mΩ maximum (the data sheet's maximum at |VGS| 2.5 V is 72.0 mΩ). At 6.43 A (the module's current and the two bucks' inputs) both parts run above their 6.0 A DC rating (5.91 A in C). By I²R, each also goes beyond the data sheet's 1 W power rating (PD, for the part on a 645 mm² copper pad), even at the typical resistance: a part reaches that rating at about 4.47 A at 50 mΩ and 4.85 A at 42.5 mΩ, and each carries 6.43 A (our arithmetic, not run). So they would heat, and their resistance would rise. Each 10 % more on both costs about 64 mV in E (59 mV in C; our arithmetic at the run's current, not run). At a constant 40 W, about 11 % more uses the whole margin: at 8.0 V the module draws 5.0 A, run D's current, and D's 70 mV margin is 11 % of its 648 mV in Q15 and Q18 (our arithmetic, not run). The true margin is almost certainly smaller once the parts heat, and possibly negative. Q15's gate is pulled to GND by R254 (10 kΩ), with Q13 as the ideal-diode control, as we read the schematic. If it sits at GND, its |VGS| is about VCC_IN (8.64 V in E). There Toshiba's 25 °C maximum is 42.0 mΩ (at VGS −10 V, ID −5.0 A): about 51 mV less in E (our arithmetic, not run; the gate drive was not computed). SCENARIO G AND U29'S CURRENT LIMIT ================================== G is a bound case, not an operating point. It asks what happens if a 5 V-only module draws a constant 25 W, the Orin Nano 8GB's 25 W* super-mode budget, while U29 sits at TI's maximum resistance over −40 to 125 °C. The module draws 5.27 A and sees 4.742 V: 8 mV below 4.75 V, NVIDIA's minimum for VDD_IN. That is about 242 mV above 4.50 V, where NVIDIA's under-voltage event (OC1) throttles the module's CPU and GPU. The carrier takes 258 mV: 237 mV in U29 at TI's 45 mΩ maximum over temperature, 6 mV in the jumpers R172 and R287 and 15 mV in copper. U29 at or below about 43.4 mΩ would put G's VDD_IN at 4.75 V (our arithmetic at G's current, not run). At TI's typical 28.2 mΩ (at VIN 12 V, IOUT 3 A, TJ 25 °C; a little higher at 5 V in TI's Figure 6-2, and TI gives no typical value for a hot part) U29 would take about 149 mV, and the module would see about 4.830 V, 80 mV above 4.75 V (our arithmetic at G's current, not run). G's 5.27 A is above the 5 A VDD_IN absolute maximum (IDDMAX) in the Orin NX data sheet whose 4.75 V row we use here. If that limit applies to a 5 V-only module, 25 W below 5.0 V (G: 5.27 A at 4.742 V) is outside NVIDIA's ratings. We did not read the Orin Nano's own data sheet. G's current is also close to U29's current limit. R283 (560 Ω) sets about 5.95 A nominal by TI's Eq. 5 (RILM = 3334 / ILIM). TI's feature list states "±10% accuracy for ILIM > 1A": about 5.36 A at the low end (our arithmetic), 1.6 % above G's current. TI's Electrical Characteristics table (−40 to 125 °C, VIN 12 V) gives "Overcurrent Threshold, RILM = 549Ω 5.400 6.068 6.600 A" (minimum, typical, maximum): a minimum 11 % below Eq. 5's 6.07 A. Scaled to 560 Ω it is about 5.29 A (our arithmetic), 0.4 % above G's current. The ITIMER pins (pad 10) of U29 and U48 are left open on this board. TI: "Leave the ITIMER pin open to allow the part to break the circuit with the minimum possible delay." (TI's data sheet (https://www.ti.com/lit/ds/symlink/tps25947.pdf)). G takes the eFuse at its maximum over temperature and the module type from a forum statement, so it is a bound case, not a finding that the board fails Super mode. The board's designer states (Antmicro, getting_started.md (https://github.com/antmicro/jetson-orin-baseboard/blob/34f0e7f5fbca441191e20ed55d93cf8614e12bed/doc/source/getting_started.md)): "The Jetson Orin Baseboard is electrically compatible with the NVIDIA Jetson Orin NX, Jetson Orin Nano family of SoMs including Super modes of those SoMs." NVIDIA applies the 25 W* budget only with its jetson-orin-nano-devkit-super flash configuration. The 5 V buck's setpoint tolerance, not modelled, moves every one of these voltages by as much as it moves the 5.0 V. All computed on the file's copper (not confirmed) at stated part resistances, not measured. WHERE THE VOLTAGE GOES: THE MODULE'S PATH ========================================= For each scenario with a 3D view: the drop budget of the module's path, then pdnsim's path step by step. A part's row is its stated resistance times the current pdnsim computes through it. A copper row is the difference between pdnsim's computed voltages at two points (pads that carry no current, then J15's pins), less the part between them, so it covers the copper on both sides of that part. The rows are made so that they add up to pdnsim's total. Scenario E: Module VDD_IN path, J12 to J15 (9 V input) ------------------------------------------------------ Where the 922.28 mV goes, for the module's 4.95 A. The path starts at J12 pad 1, held at 9.0 V, and ends at the module's pins. The rows up to the point where the path splits also carry the current of U1 (input of the carrier 5 V) and U40 (input of the carrier 3.3 V), which pdnsim computes on the same copper. - Copper from J12 pin 1 to D28 (Net-(D28-C)): 0.87 mV. pdnsim's voltages at J12 pad 1 and at D28 pad 1: 0.00 and 0.87 mV below the source, less the part(s) between. - Copper from D28 to C150 beside Q18: Net-(D28-C) to Q15, then VCC_IN: 35.56 mV. pdnsim's voltages at D28 pad 1 and at C150 pad 2: 0.87 and 357.82 mV below the source, less the part(s) between. - Q15, P-FET used as the input's ideal diode: 321.39 mV. 50 mΩ × 6.428 A. Toshiba's maximum at 25 °C and |VGS| 4.5 V, not a bound (it rises as the part heats; no maximum over temperature is stated; a pulse-test value, "Note4: Pulse test", without self-heating). Data sheet, Electrical Characteristics (Ta = 25°C), RDS (ON) typ. and max. in mΩ: "ID = -4.0 A, VGS = -4.5 V (Note 4) ― 42.5 50.0". If its gate sits at GND as we read the schematic (R254, 10 kΩ), |VGS| is about VCC_IN, where the same table gives "ID = -5.0 A, VGS = -10 V (Note 4) ― 36.0 42.0" (source: Toshiba, SSM3J332R data sheet (2018-10-15), a copy hosted by Farnell (Toshiba's own copy refused our download), https://www.farnell.com/datasheets/3622419.pdf). - Copper around Q18: C150 on VCC_IN to C50 on VCC: 1.14 mV. pdnsim's voltages at C150 pad 2 and at C50 pad 2: 357.82 and 680.35 mV below the source, less the part(s) between. - Q18, P-FET input switch: 321.39 mV. 50 mΩ × 6.428 A. Toshiba's maximum at 25 °C and |VGS| 4.5 V, not a bound (it rises as the part heats; no maximum over temperature is stated). Data sheet, Electrical Characteristics (Ta = 25°C), RDS (ON) typ. and max. in mΩ: "ID = -4.0 A, VGS = -4.5 V (Note 4) ― 42.5 50.0". Its gate sits at VCC_IN / 2 (R164 and R165, 4.7 kΩ each), so |VGS| is about 4.3 V at a 9 V input, below that 4.5 V test point (source: Toshiba, SSM3J332R data sheet (2018-10-15), a copy hosted by Farnell (Toshiba's own copy refused our download), https://www.farnell.com/datasheets/3622419.pdf). - Copper from C50 to U48 (VCC) and on from U48 to U29 pad 6 (VDD_SoM): 10.50 mV. pdnsim's voltages at C50 pad 2 and at U29 pad 6: 680.35 and 913.69 mV below the source, less the part(s) between. - U48, TPS259474 eFuse, VCC to the module (on when MODULE_ID floats: an Orin NX): 222.84 mV. 45 mΩ × 4.952 A. TI's maximum, page 9: "2.7 ≤ VIN ≤ 23V, IOUT = 3A, –40°C ≤ TJ ≤ 125°C 45 mΩ" (typical 28.2 mΩ at VIN 12 V, IOUT 3 A, TJ 25 °C; a little higher at 5 V in TI's Figure 6-2, and TI gives no typical value for a hot part) (source: Texas Instruments, TPS25947xx data sheet SLVSFC9C, https://www.ti.com/lit/ds/symlink/tps25947.pdf). - Copper around R287: U29 pad 6 on VDD_SoM to C2 on SoM_VIN: 0.89 mV. pdnsim's voltages at U29 pad 6 and at C2 pad 1: 913.69 and 917.05 mV below the source, less the part(s) between. - R287, 0 Ω jumper, VDD_SoM to SoM_VIN: 2.48 mV. 0.5 mΩ × 4.952 A. ROHM's maximum, page 1: "PMR03 1608 0603 22.4 0.5mΩ MAX．" (source: ROHM, PMR series jumper type data sheet (copy hosted by LCSC), https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/1810162127_ROHM-Semicon-PMR03EZPJ000_C253507.pdf). - Copper from C2 to J15's VDD_IN pins 251 to 260 (SoM_VIN): 2.85 mV. pdnsim's voltages at C2 pad 1 and at J15 pad 251: 917.05 and 919.91 mV below the source, less the part(s) between. - Return on GND: J15's GND pins to J12 pin 2: 2.38 mV. pdnsim's ground rise: the load's GND pins above J12 pad 2, where this rail's return leaves the copper. - Sum of the rows: 922.28 mV: parts 868.10 mV (94 %), copper 54.19 mV (6 %). - pdnsim's total drop to the module's VDD_IN: 922.28 mV: supply drop 919.91 mV plus ground rise 2.38 mV. - Check: the rows add up to 922.2828 mV and pdnsim's total is 922.2828 mV, a difference of 0.0000 mV (within 0.1 mV). - At the module: 8.0777 V between J15's VDD_IN pins and its GND pins (9.0 V less 922.28 mV). 78 mV above 8.00 V, NVIDIA's minimum VDD_IN for an Orin NX in MAXN_SUPER at 40 W. Computed, not measured. Follow the current in scenario E, step by step (pdnsim's path, as on the page): 1. The supply's + enters at J12 pin 1, held at 9.0 V (our input: the low end of Antmicro's 9 to 20 V). Copper up to D28: 0.87 mV. 2. Q15, a P-FET used as an ideal diode, carries 6.43 A: the module's 4.95 A and the two bucks' inputs. At Toshiba's 25 °C maximum of 50 mΩ it takes 321.39 mV (not a bound: at this current the part would heat and its resistance rise); the copper from D28 to C150 around it: 35.56 mV. 3. Q18, the input switch on the bottom side, another 321.39 mV at 50 mΩ (copper around it 1.14 mV). Its gate is VCC_IN / 2 (R164 and R165, 4.7 kΩ each): with VCC_IN at 8.64 V that is |VGS| = 4.32 V (our arithmetic), below the 4.5 V at which Toshiba gives the 50 mΩ maximum, so even at 25 °C its resistance may be higher. VCC then feeds the 5 V buck U1 (0.584 A) and the 3.3 V buck U40 (0.892 A): pdnsim computes these from the bucks' outputs and efficiencies. 4. U48, the eFuse that MODULE_ID turns on for an Orin NX, passes the module's 4.95 A from VCC to VDD_SoM: 222.84 mV at TI's 45 mΩ maximum; the copper from C50 through U48 to U29 pad 6: 10.50 mV. U29, the 5 V path's eFuse, blocks reverse current and is not a path in this scenario. 5. R287, a 0 Ω jumper, joins VDD_SoM to SoM_VIN: 2.48 mV, the copper around it 0.89 mV. 6. SoM_VIN copper from C2 to J15's VDD_IN pins 251 to 260: 2.85 mV. The module sees 8.0777 V between its VDD_IN and GND pins, 78 mV above 8.00 V (NVIDIA's minimum VDD_IN for an Orin NX in MAXN_SUPER at 40 W). 7. Back on GND: the module's return leaves through J15's GND pins and the GND planes to J12 pin 2: 2.38 mV. GND is one copper problem carrying every rail's return together. Scenario A: Module VDD_IN path, J12 to J15 (9 V input) ------------------------------------------------------ Where the 582.24 mV goes, for the module's 2.78 A. The path starts at J12 pad 1, held at 9.0 V, and ends at the module's pins. The rows up to the point where the path splits also carry the current of U1 (input of the carrier 5 V) and U40 (input of the carrier 3.3 V), which pdnsim computes on the same copper. - Copper from J12 pin 1 to D28 (Net-(D28-C)): 0.57 mV. pdnsim's voltages at J12 pad 1 and at D28 pad 1: 0.00 and 0.57 mV below the source, less the part(s) between. - Copper from D28 to C150 beside Q18: Net-(D28-C) to Q15, then VCC_IN: 23.32 mV. pdnsim's voltages at D28 pad 1 and at C150 pad 2: 0.57 and 234.65 mV below the source, less the part(s) between. - Q15, P-FET used as the input's ideal diode: 210.76 mV. 50 mΩ × 4.215 A. Toshiba's maximum at 25 °C and |VGS| 4.5 V, not a bound (it rises as the part heats; no maximum over temperature is stated; a pulse-test value, "Note4: Pulse test", without self-heating). Data sheet, Electrical Characteristics (Ta = 25°C), RDS (ON) typ. and max. in mΩ: "ID = -4.0 A, VGS = -4.5 V (Note 4) ― 42.5 50.0". If its gate sits at GND as we read the schematic (R254, 10 kΩ), |VGS| is about VCC_IN, where the same table gives "ID = -5.0 A, VGS = -10 V (Note 4) ― 36.0 42.0" (source: Toshiba, SSM3J332R data sheet (2018-10-15), a copy hosted by Farnell (Toshiba's own copy refused our download), https://www.farnell.com/datasheets/3622419.pdf). - Copper around Q18: C150 on VCC_IN to C50 on VCC: 0.75 mV. pdnsim's voltages at C150 pad 2 and at C50 pad 2: 234.65 and 446.16 mV below the source, less the part(s) between. - Q18, P-FET input switch: 210.76 mV. 50 mΩ × 4.215 A. Toshiba's maximum at 25 °C and |VGS| 4.5 V, not a bound (it rises as the part heats; no maximum over temperature is stated). Data sheet, Electrical Characteristics (Ta = 25°C), RDS (ON) typ. and max. in mΩ: "ID = -4.0 A, VGS = -4.5 V (Note 4) ― 42.5 50.0". Its gate sits at VCC_IN / 2 (R164 and R165, 4.7 kΩ each), so |VGS| is about 4.3 V at a 9 V input, below that 4.5 V test point (source: Toshiba, SSM3J332R data sheet (2018-10-15), a copy hosted by Farnell (Toshiba's own copy refused our download), https://www.farnell.com/datasheets/3622419.pdf). - Copper from C50 to U48 (VCC) and on from U48 to U29 pad 6 (VDD_SoM): 5.93 mV. pdnsim's voltages at C50 pad 2 and at U29 pad 6: 446.16 and 577.19 mV below the source, less the part(s) between. - U48, TPS259474 eFuse, VCC to the module (on when MODULE_ID floats: an Orin NX): 125.10 mV. 45 mΩ × 2.780 A. TI's maximum, page 9: "2.7 ≤ VIN ≤ 23V, IOUT = 3A, –40°C ≤ TJ ≤ 125°C 45 mΩ" (typical 28.2 mΩ at VIN 12 V, IOUT 3 A, TJ 25 °C; a little higher at 5 V in TI's Figure 6-2, and TI gives no typical value for a hot part) (source: Texas Instruments, TPS25947xx data sheet SLVSFC9C, https://www.ti.com/lit/ds/symlink/tps25947.pdf). - Copper around R287: U29 pad 6 on VDD_SoM to C2 on SoM_VIN: 0.50 mV. pdnsim's voltages at U29 pad 6 and at C2 pad 1: 577.19 and 579.08 mV below the source, less the part(s) between. - R287, 0 Ω jumper, VDD_SoM to SoM_VIN: 1.39 mV. 0.5 mΩ × 2.780 A. ROHM's maximum, page 1: "PMR03 1608 0603 22.4 0.5mΩ MAX．" (source: ROHM, PMR series jumper type data sheet (copy hosted by LCSC), https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/1810162127_ROHM-Semicon-PMR03EZPJ000_C253507.pdf). - Copper from C2 to J15's VDD_IN pins 251 to 260 (SoM_VIN): 1.60 mV. pdnsim's voltages at C2 pad 1 and at J15 pad 251: 579.08 and 580.68 mV below the source, less the part(s) between. - Return on GND: J15's GND pins to J12 pin 2: 1.56 mV. pdnsim's ground rise: the load's GND pins above J12 pad 2, where this rail's return leaves the copper. - Sum of the rows: 582.24 mV: parts 548.01 mV (94 %), copper 34.23 mV (6 %). - pdnsim's total drop to the module's VDD_IN: 582.24 mV: supply drop 580.68 mV plus ground rise 1.56 mV. - Check: the rows add up to 582.2385 mV and pdnsim's total is 582.2385 mV, a difference of 0.0000 mV (within 0.1 mV). - At the module: 8.4178 V between J15's VDD_IN pins and its GND pins (9.0 V less 582.24 mV). 3668 mV above 4.75 V, NVIDIA's minimum VDD_IN for a module whose MODULE_ID is high (an Orin NX). About 3918 mV above 4.50 V, NVIDIA's under-voltage throttling point for the Orin NX 16GB (its OC1 event, CPU and GPU throttled). Computed, not measured. Follow the current in scenario A, step by step (pdnsim's path, as on the page): 1. The supply's + enters at J12 pin 1, held at 9.0 V (our input: the low end of Antmicro's 9 to 20 V). Copper up to D28: 0.57 mV. 2. Q15, a P-FET used as an ideal diode, carries 4.22 A: the module's 2.78 A and the two bucks' inputs. At Toshiba's 25 °C maximum of 50 mΩ it takes 210.76 mV (not a bound: at this current the part would heat and its resistance rise); the copper from D28 to C150 around it: 23.32 mV. 3. Q18, the input switch on the bottom side, another 210.76 mV at 50 mΩ (copper around it 0.75 mV). Its gate is VCC_IN / 2 (R164 and R165, 4.7 kΩ each): with VCC_IN at 8.77 V that is |VGS| = 4.38 V (our arithmetic), below the 4.5 V at which Toshiba gives the 50 mΩ maximum, so even at 25 °C its resistance may be higher. VCC then feeds the 5 V buck U1 (0.568 A) and the 3.3 V buck U40 (0.868 A): pdnsim computes these from the bucks' outputs and efficiencies. 4. U48, the eFuse that MODULE_ID turns on for an Orin NX, passes the module's 2.78 A from VCC to VDD_SoM: 125.10 mV at TI's 45 mΩ maximum; the copper from C50 through U48 to U29 pad 6: 5.93 mV. U29, the 5 V path's eFuse, blocks reverse current and is not a path in this scenario. 5. R287, a 0 Ω jumper, joins VDD_SoM to SoM_VIN: 1.39 mV, the copper around it 0.50 mV. 6. SoM_VIN copper from C2 to J15's VDD_IN pins 251 to 260: 1.60 mV. The module sees 8.4178 V between its VDD_IN and GND pins, 3668 mV above 4.75 V (NVIDIA's minimum VDD_IN for a module whose MODULE_ID is high (an Orin NX)). 7. Back on GND: the module's return leaves through J15's GND pins and the GND planes to J12 pin 2: 1.56 mV. GND is one copper problem carrying every rail's return together. Scenario B: Module VDD_IN path, L4 through U29 to J15 (5 V) ----------------------------------------------------------- Where the 147.81 mV goes, for the module's 3.00 A. The path starts at L4 pad 2, held at 5.0 V, and ends at the module's pins. The rows up to the point where the path splits also carry the current of USB-C1's VBUS load, which pdnsim computes on the same copper. - Copper from L4 pad 2 to C129 (5V_OUT): 2.98 mV. pdnsim's voltages at L4 pad 2 and at C129 pad 2: 0.00 and 2.98 mV below the source, less the part(s) between. - Copper around R172: C129 on 5V_OUT to D32 on +5V_SoM: 1.98 mV. pdnsim's voltages at C129 pad 2 and at D32 pad 1: 2.98 and 6.91 mV below the source, less the part(s) between. - R172, 0 Ω jumper, 5V_OUT to +5V_SoM: 1.95 mV. 0.5 mΩ × 3.900 A. ROHM's maximum, page 1: "PMR03 1608 0603 22.4 0.5mΩ MAX．" (source: ROHM, PMR series jumper type data sheet (copy hosted by LCSC), https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/1810162127_ROHM-Semicon-PMR03EZPJ000_C253507.pdf). - Copper from D32 to C2: +5V_SoM to U29, VDD_SoM to R287, then SoM_VIN: 1.70 mV. pdnsim's voltages at D32 pad 1 and at C2 pad 1: 6.91 and 145.11 mV below the source, less the part(s) between. - U29, TPS259474 eFuse, +5V_SoM to the module (always on): 135.00 mV. 45 mΩ × 3.000 A. TI's maximum, page 9: "2.7 ≤ VIN ≤ 23V, IOUT = 3A, –40°C ≤ TJ ≤ 125°C 45 mΩ" (typical 28.2 mΩ at VIN 12 V, IOUT 3 A, TJ 25 °C; a little higher at 5 V in TI's Figure 6-2, and TI gives no typical value for a hot part) (source: Texas Instruments, TPS25947xx data sheet SLVSFC9C, https://www.ti.com/lit/ds/symlink/tps25947.pdf). - R287, 0 Ω jumper, VDD_SoM to SoM_VIN: 1.50 mV. 0.5 mΩ × 3.000 A. ROHM's maximum, page 1: "PMR03 1608 0603 22.4 0.5mΩ MAX．" (source: ROHM, PMR series jumper type data sheet (copy hosted by LCSC), https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/1810162127_ROHM-Semicon-PMR03EZPJ000_C253507.pdf). - Copper from C2 to J15's VDD_IN pins 251 to 260 (SoM_VIN): 1.73 mV. pdnsim's voltages at C2 pad 1 and at J15 pad 251: 145.11 and 146.84 mV below the source, less the part(s) between. - Return on GND: J15's GND pins to U1's GND pads: 0.98 mV. pdnsim's ground rise: the load's GND pins above U1's GND pads, where this rail's return leaves the copper. - Sum of the rows: 147.81 mV: parts 138.45 mV (94 %), copper 9.36 mV (6 %). - pdnsim's total drop to the module's VDD_IN: 147.81 mV: supply drop 146.84 mV plus ground rise 0.98 mV. - Check: the rows add up to 147.8125 mV and pdnsim's total is 147.8125 mV, a difference of 0.0000 mV (within 0.1 mV). - At the module: 4.8522 V between J15's VDD_IN pins and its GND pins (5.0 V less 147.81 mV). 102 mV above 4.75 V, NVIDIA's minimum VDD_IN for a module whose MODULE_ID is low (a 5 V-only module). About 352 mV above 4.50 V, NVIDIA's under-voltage throttling point for the Orin Nano 8GB (its OC1 event). Computed, not measured. Follow the current in scenario B, step by step (pdnsim's path, as on the page): 1. U1's 5 V output enters the copper at L4 pad 2, held at 5.0 V (U1's setpoint; its tolerance and load regulation are not modelled). Copper to C129: 2.98 mV. 2. R172, a 0 Ω jumper, carries 3.90 A: the module's 3.00 A and USB-C1's 0.90 A. 1.95 mV; the copper around it 1.98 mV. 3. On +5V_SoM, Q6 on the bottom side branches off the carrier's own +5V (USB-C1's 0.90 A, 45.0 mV across Q6); it is not on the module's path. 4. U29, the eFuse that feeds a 5 V-only module (its MODULE_ID tied to GND keeps U48 off), takes 135.00 mV at TI's 45 mΩ maximum over temperature (about 85 mV at TI's typical 28.2 mΩ, at VIN 12 V, IOUT 3 A, TJ 25 °C; a little higher at 5 V in TI's Figure 6-2, and TI gives no typical value for a hot part: our arithmetic, not run). R287 adds 1.50 mV; the copper from D32 to C2: 1.70 mV. U29's current limit, set by R283 (560 Ω), is about 5.95 A nominal by TI's Eq. 5 (RILM = 3334 / ILIM). TI's feature list states ±10 %, about 5.36 A at the low end (our arithmetic), 79 % above the module's 3.00 A; TI's Electrical Characteristics table gives 5.400 A minimum at RILM = 549 Ω (VIN 12 V, TJ −40 to 125 °C), which scaled to 560 Ω is about 5.29 A (our arithmetic), 76 % above it. U29's ITIMER pin (pad 10) is left open, so this circuit breaker acts with the minimum possible delay (TI: "Leave the ITIMER pin open to allow the part to break the circuit with the minimum possible delay."). 5. SoM_VIN copper from C2 to J15's VDD_IN pins: 1.73 mV. The module sees 4.8522 V between its VDD_IN and GND pins, 102 mV above 4.75 V (NVIDIA's minimum VDD_IN for a module whose MODULE_ID is low (a 5 V-only module)). 6. Back on GND to U1's GND pads: 0.98 mV. GND is one copper problem carrying every rail's return together. Scenario G: Module VDD_IN path, L4 through U29 to J15 (5 V) ----------------------------------------------------------- Where the 258.40 mV goes, for the module's 5.27 A. The path starts at L4 pad 2, held at 5.0 V, and ends at the module's pins. The rows up to the point where the path splits also carry the current of USB-C1's VBUS load, which pdnsim computes on the same copper. - Copper from L4 pad 2 to C129 (5V_OUT): 4.72 mV. pdnsim's voltages at L4 pad 2 and at C129 pad 2: 0.00 and 4.72 mV below the source, less the part(s) between. - Copper around R172: C129 on 5V_OUT to D32 on +5V_SoM: 2.97 mV. pdnsim's voltages at C129 pad 2 and at D32 pad 1: 4.72 and 10.77 mV below the source, less the part(s) between. - R172, 0 Ω jumper, 5V_OUT to +5V_SoM: 3.09 mV. 0.5 mΩ × 6.173 A. ROHM's maximum, page 1: "PMR03 1608 0603 22.4 0.5mΩ MAX．" (source: ROHM, PMR series jumper type data sheet (copy hosted by LCSC), https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/1810162127_ROHM-Semicon-PMR03EZPJ000_C253507.pdf). - Copper from D32 to C2: +5V_SoM to U29, VDD_SoM to R287, then SoM_VIN: 3.20 mV. pdnsim's voltages at D32 pad 1 and at C2 pad 1: 10.77 and 253.88 mV below the source, less the part(s) between. - U29, TPS259474 eFuse, +5V_SoM to the module (always on): 237.27 mV. 45 mΩ × 5.273 A. TI's maximum, page 9: "2.7 ≤ VIN ≤ 23V, IOUT = 3A, –40°C ≤ TJ ≤ 125°C 45 mΩ" (typical 28.2 mΩ at VIN 12 V, IOUT 3 A, TJ 25 °C; a little higher at 5 V in TI's Figure 6-2, and TI gives no typical value for a hot part) (source: Texas Instruments, TPS25947xx data sheet SLVSFC9C, https://www.ti.com/lit/ds/symlink/tps25947.pdf). - R287, 0 Ω jumper, VDD_SoM to SoM_VIN: 2.64 mV. 0.5 mΩ × 5.273 A. ROHM's maximum, page 1: "PMR03 1608 0603 22.4 0.5mΩ MAX．" (source: ROHM, PMR series jumper type data sheet (copy hosted by LCSC), https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/1810162127_ROHM-Semicon-PMR03EZPJ000_C253507.pdf). - Copper from C2 to J15's VDD_IN pins 251 to 260 (SoM_VIN): 3.04 mV. pdnsim's voltages at C2 pad 1 and at J15 pad 251: 253.88 and 256.92 mV below the source, less the part(s) between. - Return on GND: J15's GND pins to U1's GND pads: 1.48 mV. pdnsim's ground rise: the load's GND pins above U1's GND pads, where this rail's return leaves the copper. - Sum of the rows: 258.40 mV: parts 242.99 mV (94 %), copper 15.41 mV (6 %). - pdnsim's total drop to the module's VDD_IN: 258.40 mV: supply drop 256.92 mV plus ground rise 1.48 mV. - Check: the rows add up to 258.3971 mV and pdnsim's total is 258.3971 mV, a difference of 0.0000 mV (within 0.1 mV). - At the module: 4.7416 V between J15's VDD_IN pins and its GND pins (5.0 V less 258.40 mV). 8 mV below 4.75 V, NVIDIA's minimum VDD_IN for a module whose MODULE_ID is low (a 5 V-only module). About 242 mV above 4.50 V, NVIDIA's under-voltage throttling point for the Orin Nano 8GB (its OC1 event). Computed, not measured. Follow the current in scenario G, step by step (pdnsim's path, as on the page): 1. U1's 5 V output enters the copper at L4 pad 2, held at 5.0 V (U1's setpoint; its tolerance and load regulation are not modelled). Copper to C129: 4.72 mV. 2. R172, a 0 Ω jumper, carries 6.17 A: the module's 5.27 A and USB-C1's 0.90 A. 3.09 mV; the copper around it 2.97 mV. 3. On +5V_SoM, Q6 on the bottom side branches off the carrier's own +5V (USB-C1's 0.90 A, 45.0 mV across Q6); it is not on the module's path. 4. U29, the eFuse that feeds a 5 V-only module (its MODULE_ID tied to GND keeps U48 off), takes 237.27 mV at TI's 45 mΩ maximum over temperature (about 149 mV at TI's typical 28.2 mΩ, at VIN 12 V, IOUT 3 A, TJ 25 °C; a little higher at 5 V in TI's Figure 6-2, and TI gives no typical value for a hot part: our arithmetic, not run). R287 adds 2.64 mV; the copper from D32 to C2: 3.20 mV. U29's current limit, set by R283 (560 Ω), is about 5.95 A nominal by TI's Eq. 5 (RILM = 3334 / ILIM). TI's feature list states ±10 %, about 5.36 A at the low end (our arithmetic), 1.6 % above the module's 5.27 A; TI's Electrical Characteristics table gives 5.400 A minimum at RILM = 549 Ω (VIN 12 V, TJ −40 to 125 °C), which scaled to 560 Ω is about 5.29 A (our arithmetic), 0.4 % above it. U29's ITIMER pin (pad 10) is left open, so this circuit breaker acts with the minimum possible delay (TI: "Leave the ITIMER pin open to allow the part to break the circuit with the minimum possible delay."). 5. SoM_VIN copper from C2 to J15's VDD_IN pins: 3.04 mV. The module sees 4.7416 V between its VDD_IN and GND pins, 8 mV below 4.75 V (NVIDIA's minimum VDD_IN for a module whose MODULE_ID is low (a 5 V-only module)). 6. Back on GND to U1's GND pads: 1.48 mV. GND is one copper problem carrying every rail's return together. WHY THERE IS NO VERDICT ======================= pdnsim gives no pass or fail on this board. Two things stop it. 1. The copper thickness is not confirmed. The board file gives all eight copper layers KiCad's default 35 µm. The file cannot tell a value someone entered from KiCad's default, and we have no fab stackup for this board, so we did not state the thickness either. The copper's drops scale with 1/thickness, so pdnsim gives no rail a verdict on a guess. 2. We turned judging off ourselves. We set judge: false on every rail, because this is a third-party board, analysed unmodified, in scenarios we chose, not the designer's. Scenario E: pdnsim's status line (its separators written as commas): NO VERDICT, 0 exclusions, 3 not judged. It labels the module's numbers "at average current, not a verdict": the module's current comes from a mode's power read from the mode's name in NVIDIA's data sheet (a budget, not a stated draw; NVIDIA calls MAXN an unconstrained mode that throttles at its TDP budget), as the current at which the module receives 40 W, entered as an average current, so pdnsim withholds losses in watts, and its rule-of-thumb (heuristic) flags are not verdicts. The numbers are still computed and shown. Scenario A: pdnsim's status line (its separators written as commas): NO VERDICT, 0 exclusions, 3 not judged. It labels the module's numbers "at average current, not a verdict": the module's current comes from a mode's average-power budget in NVIDIA's r36.4 table (a budget, an upper bound, not a stated draw), over the 9.0 V input, entered as an average current, so pdnsim withholds losses in watts, and its rule-of-thumb (heuristic) flags are not verdicts. The numbers are still computed and shown. Scenario B: pdnsim's status line (its separators written as commas): NO VERDICT, 0 exclusions, 3 not judged. It labels the module's numbers "at average current, not a verdict": the module's current comes from a mode's average-power budget in NVIDIA's r36.4 table (a budget, an upper bound, not a stated draw), over the 5.0 V setpoint, entered as an average current, so pdnsim withholds losses in watts, and its rule-of-thumb (heuristic) flags are not verdicts. The numbers are still computed and shown. Scenario G: pdnsim's status line (its separators written as commas): NO VERDICT, 0 exclusions, 3 not judged. It labels the module's numbers "at average current, not a verdict": the module's current comes from a mode's average-power budget in NVIDIA's r36.4 table (a budget, an upper bound, not a stated draw), as the current at which the module receives 25 W, entered as an average current, so pdnsim withholds losses in watts, and its rule-of-thumb (heuristic) flags are not verdicts. The numbers are still computed and shown. In the status line, "not judged" counts the rails set not to be judged, and "exclusions" counts currents the configuration leaves out of the model, such as a load set to 0 A. pdnsim's reasons, in its own words (every scenario): BOARD_COPPER_PLACEHOLDER: a copper weight is KiCad's default 35 µm, not a stated value: the board file's stackup gives copper layers F.Cu, In1.Cu, In2.Cu, In3.Cu, In4.Cu, In5.Cu, In6.Cu and B.Cu exactly KiCad's default 35 µm, which KiCad writes the same whether someone entered it or KiCad generated it (the file cannot tell a stated 35 µm from KiCad's default), and the configuration does not state the thickness of copper layers F.Cu, In1.Cu, In2.Cu, In3.Cu, In4.Cu, In5.Cu, In6.Cu and B.Cu. The drops scale with 1/thickness, so no rail gets a verdict on a guessed copper weight. Add the finished copper thickness of each layer from the fab's stackup, in µm (a weight in oz is not a thickness), in place of each ‹µm› — add these lines at the top level of the configuration file (it has no `copper:` key yet): copper: thickness_override_um: F.Cu: ‹µm› In1.Cu: ‹µm› In2.Cu: ‹µm› In3.Cu: ‹µm› In4.Cu: ‹µm› In5.Cu: ‹µm› In6.Cu: ‹µm› B.Cu: ‹µm› Or enter the fab's stackup in KiCad (Board Setup › Physical Stackup) and save the board (a copper layer of exactly 35 µm still reads as KiCad's default, whatever the rest of the stackup says: then state that layer here). A basis alone does not lift this: every layer needs its value. With every layer stated, the verdict reads 'copper not confirmed as built' until copper.thickness and copper.via_plating_um carry a basis of an as-built kind (fab_stackup, order_spec or measured) CONFIG_NOTHING_JUDGED: every rail has judge: false: nothing is judged, so the run has no verdict (the numbers are shown) WHAT PDNSIM FLAGS ON THE MODULE'S PATH ====================================== pdnsim's own findings, verbatim from each scenario's results.json. Suggestions are changes pdnsim proposes, such as wider copper or more vias. Bottlenecks are the places with the largest share of the loss, on this rail and on GND. Every current-density and via limit in them is a heuristic: a rule of thumb, never a pass or fail. Where a finding ends with "(at average current, not a verdict: …)", pdnsim means that the current it was given is an average, so it does not treat that flag as a pass or fail. Labels: S2 is a suggestion, B2 a bottleneck on this rail, and GND B2 a bottleneck on GND. Sentences end at "…" where the rest refers to pdnsim's default 3 % drop limit, which no one set for this board. Scenario E: 12 suggestions and 20 bottlenecks --------------------------------------------- - [S2, link resistance, Module VDD_IN path] U48 (load switch, 45 mΩ (config, given)) carries 4.95 A and drops 223 mV — 24 % of SoM_VDD_IN's total drop (922 mV) … - [S3, link resistance, Module VDD_IN path] R287 (jumper, 0.5 mΩ (config, given)) carries 4.95 A and drops 2.48 mV — 0 % of SoM_VDD_IN's total drop (922 mV) … - [S4, via current, Module VDD_IN path] 6 vias (In1.Cu → B.Cu) at (44.80, 81.60) mm on /Supply/VCC_IN carry 6.43 A in total; 6 of them exceed the heuristic 1 A per-via limit (most loaded: via #1050, 1.16 A). If the current shared equally between parallel barrels, 7 vias (add 1 next to these) would keep each under the limit; here the 6 vias share it unevenly (1.16 A vs a mean of 1.07 A): rerun the analysis after adding vias to confirm. The limit is a heuristic (thermal/reliability), not a physical threshold. (at average current, not a verdict: the current-basis gate withholds heuristic flags here) - [S5, via current, GND] The plated hole of J3 pad SH (In4.Cu → F.Cu) at (49.27, 125.99) mm on GND carries 1.03 A, above the heuristic 1 A per-via limit. If the current shared equally between parallel barrels, the hole plus 1 via(s) next to it would keep each under the limit; rerun the analysis after adding them to confirm the sharing. The limit is a heuristic (thermal/reliability), not a physical threshold. (at average current, not a verdict: the current-basis gate withholds heuristic flags here) - [S6, current density, Module VDD_IN path] Narrow passage in zone VCC on B.Cu (VCC, about 0.61 mm wide) near (51.63, 80.79) mm reaches 542 A/mm² at (51.66, 80.81) mm (averaged over 0.1 mm), above the heuristic 35 A/mm² limit. At the same current the density falls roughly in proportion to the width: about ×15.48 wider copper there meets it. The limit is a heuristic (it depends on cooling and reliability targets). (at average current, not a verdict: the current-basis gate withholds heuristic flags here) - [S7, current density, Module VDD_IN path] Narrow passage in zone VDD_SoM on B.Cu (VDD_SoM, about 0.4 mm wide) near (51.58, 81.36) mm reaches 389 A/mm² at (51.66, 81.36) mm (averaged over 0.1 mm), above the heuristic 35 A/mm² limit. At the same current the density falls roughly in proportion to the width: about ×11.12 wider copper there meets it. The limit is a heuristic (it depends on cooling and reliability targets). (at average current, not a verdict: the current-basis gate withholds heuristic flags here) - [S8, current density, Module VDD_IN path] Narrow passage in zone Net-(D28-C) on F.Cu (Net-(D28-C), about 0.32 mm wide) near (55.17, 116.31) mm reaches 130 A/mm² at (55.16, 116.13) mm (averaged over 0.1 mm), above the heuristic 35 A/mm² limit. At the same current the density falls roughly in proportion to the width: about ×3.72 wider copper there meets it. The limit is a heuristic (it depends on cooling and reliability targets). (at average current, not a verdict: the current-basis gate withholds heuristic flags here) - [S9, current density, Module VDD_IN path] Narrow passage in zone Net-(D28-C) on F.Cu (Net-(D28-C), about 0.76 mm wide) near (54.17, 115.47) mm reaches 72 A/mm² at (54.53, 115.02) mm (averaged over 0.1 mm), above the heuristic 35 A/mm² limit. At the same current the density falls roughly in proportion to the width: about ×2.06 wider copper there meets it. The limit is a heuristic (it depends on cooling and reliability targets). (at average current, not a verdict: the current-basis gate withholds heuristic flags here) - [S10, current density, Module VDD_IN path] Narrow passage in zone /Supply/VCC_IN on In1.Cu (/Supply/VCC_IN, about 0.31 mm wide) near (57.52, 103.80) mm reaches 62.9 A/mm² at (57.43, 103.68) mm (averaged over 0.1 mm), above the heuristic 35 A/mm² limit. At the same current the density falls roughly in proportion to the width: about ×1.80 wider copper there meets it. The limit is a heuristic (it depends on cooling and reliability targets). (2 more trace/neck feature(s) on Net-(D28-C) + /SoM/SoM_VIN + /Supply/VCC_IN + VCC + VDD_SoM are above the limit.) (at average current, not a verdict: the current-basis gate withholds heuristic flags here) - [S11, current density, Module VDD_IN path] The current density on F.Cu (Net-(D28-C) + /SoM/SoM_VIN + /Supply/VCC_IN + VCC + VDD_SoM) reaches 161 A/mm² at (56.94, 111.08) mm, above the heuristic 35 A/mm² limit (averaged over 0.1 mm). Spread the current there: more copper, more or larger vias, or a larger contact. The limit is a heuristic. (at average current, not a verdict: the current-basis gate withholds heuristic flags here) - [S12, current density, Module VDD_IN path] The current density on In1.Cu (Net-(D28-C) + /SoM/SoM_VIN + /Supply/VCC_IN + VCC + VDD_SoM) reaches 106 A/mm² at (45.01, 82.45) mm, above the heuristic 35 A/mm² limit (averaged over 0.1 mm). Spread the current there: more copper, more or larger vias, or a larger contact. The limit is a heuristic. (at average current, not a verdict: the current-basis gate withholds heuristic flags here) - [S13, current density, GND] Trace B4 on F.Cu (GND) from U18 pad 2 (102.35, 120.55) mm to via #390 (102.05, 119.25) mm, 0.3 mm wide in 35 µm copper, carries up to 0.9 A: 85.7 A/mm² in the trace body (up to 103 A/mm² at (102.21, 119.64) mm, averaged over 0.1 mm), above the heuristic 35 A/mm² limit. A width of at least 0.735 mm (I/(J_limit×t)) brings the trace body to the limit at this current. Where the current turns or enters a pad or via the density is 1.21× the body value here, so such spots stay above the limit unless they are widened too. The limit is a heuristic (it depends on cooling and reliability targets). (at average current, not a verdict: the current-basis gate withholds heuristic flags here) - [B1, link, Module VDD_IN path] Series link Q15 at (57.73, 112.60) mm: 37.1% share of loss. - [B2, link, Module VDD_IN path] Series link Q18 at (49.62, 79.63) mm: 37.1% share of loss. - [B3, link, Module VDD_IN path] Series link U48 at (52.88, 81.08) mm: 19.8% share of loss. - [B4, via cluster, Module VDD_IN path] Cluster of 6 vias (0.1 mm drill, In1.Cu → B.Cu) around (44.80, 81.60) mm: 6.43 A in total, up to 1.16 A per via, 5.74 mV across the barrels; 0.6% share of loss. - [B5, plane region, Module VDD_IN path] zone /Supply/VCC_IN on In1.Cu copper in a 3.51 × 3.51 mm area, loss centred near (45.69, 82.21) mm: 3.08 mV across the area, up to 106 A/mm²; 0.2% share of loss. - [B6, link, Module VDD_IN path] Series link R287 at (57.30, 87.50) mm: 0.2% share of loss. - [B7, plane region, Module VDD_IN path] zone /Supply/VCC_IN on B.Cu copper in a 2 × 2 mm area, loss centred near (44.73, 80.09) mm: 2.64 mV across the area, up to 140 A/mm²; 0.2% share of loss. - [B8, via cluster, Module VDD_IN path] Cluster of 6 vias (0.1 mm drill, B.Cu → F.Cu) around (50.36, 81.74) mm near C50: 3.61 A in total, up to 0.62 A per via, 3.19 mV across the barrels; 0.2% share of loss. - [B9, plane region, Module VDD_IN path] zone Net-(D28-C) on F.Cu copper in a 2 × 2 mm area, loss centred near (57.01, 115.69) mm: 3.42 mV across the area, up to 92.1 A/mm²; 0.2% share of loss. - [B10, plane region, Module VDD_IN path] zone /Supply/VCC_IN on B.Cu copper in a 2 × 2 mm area, loss centred near (46.16, 79.94) mm near C150, R164: 4.04 mV across the area, up to 178 A/mm²; 0.2% share of loss. - [GND B1, via, GND] Via #390 (0.1 mm drill, F.Cu → In6.Cu) at (102.05, 119.25) mm: 0.9 A, 4.58 mV across the barrel; 19.2% share of loss. - [GND B2, via cluster, GND] Cluster of 7 vias (0.1 mm drill, In1.Cu → F.Cu) around (51.70, 119.40) mm near J12, U11: 3.28 A in total, up to 0.844 A per via, 1.02 mV across the barrels; 7.5% share of loss. - [GND B3, plane region, GND] zone GND on F.Cu copper in a 2 × 2 mm area, loss centred near (51.71, 119.04) mm near J12: 0.454 mV across the area, up to 93.5 A/mm²; 4.8% share of loss. - [GND B4, trace, GND] Trace on F.Cu, 0.3 mm wide and 0.619 mm long (outside pads, vias and zones) from U18 pad 2 (102.35, 120.55) mm to via #390 (102.05, 119.25) mm: 0.885 mV across it at 0.9 A, up to 103 A/mm²; 3.7% share of loss. - [GND B5, plane region, GND] zone GND on In1.Cu copper in a 10 × 9.2 mm area, loss centred near (54.49, 121.87) mm near D6, D53, J3, J12, U11: 0.603 mV across the area, up to 19.6 A/mm²; 2.8% share of loss. - [GND B6, plane region, GND] zone GND on F.Cu copper in a 2 × 0.8 mm area, loss centred near (51.59, 120.16) mm: 0.513 mV across the area, up to 95.3 A/mm²; 2.5% share of loss. - [GND B7, plane region, GND] zone GND on In1.Cu copper in a 10 × 10 mm area, loss centred near (54.21, 116.98) mm near C29, C145, C146, D28, U5: 0.601 mV across the area, up to 13.4 A/mm²; 2.1% share of loss. - [GND B8, plane region, GND] zone GND on F.Cu copper in a 2 × 0.8 mm area, loss centred near (50.56, 120.16) mm: 0.312 mV across the area, up to 51.5 A/mm²; 1.6% share of loss. - [GND B9, via cluster, GND] Cluster of 6 vias (0.1 mm drill, In4.Cu → F.Cu) around (50.50, 118.80) mm near Q21: 0.964 A in total, up to 0.187 A per via, 0.473 mV across the barrels; 1.4% share of loss. - [GND B10, plane region, GND] zone GND on In4.Cu copper in a 10 × 10 mm area, loss centred near (54.29, 114.89) mm near C29, C145, C146, D28, U5: 0.552 mV across the area, up to 8.8 A/mm²; 1.2% share of loss. Left out: S1 (measured against the default 3 % limit). Scenario A: 10 suggestions and 20 bottlenecks --------------------------------------------- - [S2, link resistance, Module VDD_IN path] U48 (load switch, 45 mΩ (config, given)) carries 2.78 A and drops 125 mV — 21 % of SoM_VDD_IN's total drop (582 mV) … - [S3, link resistance, Module VDD_IN path] R287 (jumper, 0.5 mΩ (config, given)) carries 2.78 A and drops 1.39 mV — 0 % of SoM_VDD_IN's total drop (582 mV) … - [S4, current density, Module VDD_IN path] Narrow passage in zone VCC on B.Cu (VCC, about 0.61 mm wide) near (51.63, 80.79) mm reaches 314 A/mm² at (51.66, 80.81) mm (averaged over 0.1 mm), above the heuristic 35 A/mm² limit. At the same current the density falls roughly in proportion to the width: about ×8.97 wider copper there meets it. The limit is a heuristic (it depends on cooling and reliability targets). (at average current, not a verdict: the current-basis gate withholds heuristic flags here) - [S5, current density, Module VDD_IN path] Narrow passage in zone VDD_SoM on B.Cu (VDD_SoM, about 0.4 mm wide) near (51.58, 81.36) mm reaches 219 A/mm² at (51.66, 81.36) mm (averaged over 0.1 mm), above the heuristic 35 A/mm² limit. At the same current the density falls roughly in proportion to the width: about ×6.24 wider copper there meets it. The limit is a heuristic (it depends on cooling and reliability targets). (at average current, not a verdict: the current-basis gate withholds heuristic flags here) - [S6, current density, Module VDD_IN path] Narrow passage in zone Net-(D28-C) on F.Cu (Net-(D28-C), about 0.32 mm wide) near (55.17, 116.31) mm reaches 85.5 A/mm² at (55.16, 116.13) mm (averaged over 0.1 mm), above the heuristic 35 A/mm² limit. At the same current the density falls roughly in proportion to the width: about ×2.44 wider copper there meets it. The limit is a heuristic (it depends on cooling and reliability targets). (at average current, not a verdict: the current-basis gate withholds heuristic flags here) - [S7, current density, Module VDD_IN path] Narrow passage in zone Net-(D28-C) on F.Cu (Net-(D28-C), about 0.76 mm wide) near (54.17, 115.47) mm reaches 47.2 A/mm² at (54.53, 115.02) mm (averaged over 0.1 mm), above the heuristic 35 A/mm² limit. At the same current the density falls roughly in proportion to the width: about ×1.35 wider copper there meets it. The limit is a heuristic (it depends on cooling and reliability targets). (at average current, not a verdict: the current-basis gate withholds heuristic flags here) - [S8, current density, Module VDD_IN path] Narrow passage in zone /Supply/VCC_IN on In1.Cu (/Supply/VCC_IN, about 0.31 mm wide) near (57.52, 103.80) mm reaches 41.3 A/mm² at (57.43, 103.68) mm (averaged over 0.1 mm), above the heuristic 35 A/mm² limit. At the same current the density falls roughly in proportion to the width: about ×1.18 wider copper there meets it. The limit is a heuristic (it depends on cooling and reliability targets). (at average current, not a verdict: the current-basis gate withholds heuristic flags here) - [S9, current density, Module VDD_IN path] The current density on F.Cu (Net-(D28-C) + /SoM/SoM_VIN + /Supply/VCC_IN + VCC + VDD_SoM) reaches 105 A/mm² at (56.94, 111.08) mm, above the heuristic 35 A/mm² limit (averaged over 0.1 mm). Spread the current there: more copper, more or larger vias, or a larger contact. The limit is a heuristic. (at average current, not a verdict: the current-basis gate withholds heuristic flags here) - [S10, current density, Module VDD_IN path] The current density on In1.Cu (Net-(D28-C) + /SoM/SoM_VIN + /Supply/VCC_IN + VCC + VDD_SoM) reaches 69.4 A/mm² at (45.01, 82.45) mm, above the heuristic 35 A/mm² limit (averaged over 0.1 mm). Spread the current there: more copper, more or larger vias, or a larger contact. The limit is a heuristic. (at average current, not a verdict: the current-basis gate withholds heuristic flags here) - [S11, current density, GND] Trace B2 on F.Cu (GND) from U18 pad 2 (102.35, 120.55) mm to via #390 (102.05, 119.25) mm, 0.3 mm wide in 35 µm copper, carries up to 0.9 A: 85.7 A/mm² in the trace body (up to 103 A/mm² at (102.21, 119.64) mm, averaged over 0.1 mm), above the heuristic 35 A/mm² limit. A width of at least 0.735 mm (I/(J_limit×t)) brings the trace body to the limit at this current. Where the current turns or enters a pad or via the density is 1.21× the body value here, so such spots stay above the limit unless they are widened too. The limit is a heuristic (it depends on cooling and reliability targets). (at average current, not a verdict: the current-basis gate withholds heuristic flags here) - [B1, link, Module VDD_IN path] Series link Q15 at (57.73, 112.60) mm: 39.3% share of loss. - [B2, link, Module VDD_IN path] Series link Q18 at (49.62, 79.63) mm: 39.3% share of loss. - [B3, link, Module VDD_IN path] Series link U48 at (52.88, 81.08) mm: 15.4% share of loss. - [B4, via cluster, Module VDD_IN path] Cluster of 6 vias (0.1 mm drill, In1.Cu → B.Cu) around (44.80, 81.60) mm: 4.22 A in total, up to 0.761 A per via, 3.76 mV across the barrels; 0.6% share of loss. - [B5, plane region, Module VDD_IN path] zone /Supply/VCC_IN on In1.Cu copper in a 3.51 × 3.51 mm area, loss centred near (45.69, 82.21) mm: 2.02 mV across the area, up to 69.4 A/mm²; 0.3% share of loss. - [B6, plane region, Module VDD_IN path] zone /Supply/VCC_IN on B.Cu copper in a 2 × 2 mm area, loss centred near (44.73, 80.09) mm: 1.73 mV across the area, up to 92 A/mm²; 0.2% share of loss. - [B7, plane region, Module VDD_IN path] zone Net-(D28-C) on F.Cu copper in a 2 × 2 mm area, loss centred near (57.01, 115.69) mm: 2.25 mV across the area, up to 60.4 A/mm²; 0.2% share of loss. - [B8, plane region, Module VDD_IN path] zone /Supply/VCC_IN on B.Cu copper in a 2 × 2 mm area, loss centred near (46.16, 79.94) mm near C150, R164: 2.65 mV across the area, up to 117 A/mm²; 0.2% share of loss. - [B9, plane region, Module VDD_IN path] zone /Supply/VCC_IN on In1.Cu copper in a 3.51 × 3.51 mm area, loss centred near (48.72, 85.61) mm: 1.94 mV across the area, up to 32.3 A/mm²; 0.2% share of loss. - [B10, link, Module VDD_IN path] Series link R287 at (57.30, 87.50) mm: 0.2% share of loss. - [GND B1, via, GND] Via #390 (0.1 mm drill, F.Cu → In6.Cu) at (102.05, 119.25) mm: 0.9 A, 4.58 mV across the barrel; 32.3% share of loss. - [GND B2, trace, GND] Trace on F.Cu, 0.3 mm wide and 0.619 mm long (outside pads, vias and zones) from U18 pad 2 (102.35, 120.55) mm to via #390 (102.05, 119.25) mm: 0.885 mV across it at 0.9 A, up to 103 A/mm²; 6.3% share of loss. - [GND B3, via cluster, GND] Cluster of 7 vias (0.1 mm drill, In1.Cu → F.Cu) around (51.70, 119.40) mm near J12, U11: 2.15 A in total, up to 0.554 A per via, 0.667 mV across the barrels; 5.4% share of loss. - [GND B4, plane region, GND] zone GND on F.Cu copper in a 2 × 2 mm area, loss centred near (51.71, 119.04) mm near J12: 0.297 mV across the area, up to 61.3 A/mm²; 3.5% share of loss. - [GND B5, plane region, GND] zone GND on In1.Cu copper in a 10 × 9.2 mm area, loss centred near (54.49, 121.87) mm near D6, D53, J3, J12, U11: 0.397 mV across the area, up to 12.9 A/mm²; 2.1% share of loss. - [GND B6, plane region, GND] zone GND on F.Cu copper in a 2 × 0.8 mm area, loss centred near (51.59, 120.16) mm: 0.336 mV across the area, up to 62.5 A/mm²; 1.8% share of loss. - [GND B7, plane region, GND] zone GND on In1.Cu copper in a 10 × 10 mm area, loss centred near (54.21, 116.98) mm near C29, C145, C146, D28, U5: 0.395 mV across the area, up to 8.8 A/mm²; 1.5% share of loss. - [GND B8, plane region, GND] zone GND on F.Cu copper in a 2 × 0.8 mm area, loss centred near (50.56, 120.16) mm: 0.205 mV across the area, up to 33.7 A/mm²; 1.1% share of loss. - [GND B9, plane region, GND] zone GND on In6.Cu copper in a 10 × 9.2 mm area, loss centred near (102.06, 120.59) mm near C74, C75, D11, D55, J5: 0.308 mV across the area, up to 16.1 A/mm²; 1.0% share of loss. - [GND B10, via cluster, GND] Cluster of 6 vias (0.1 mm drill, In4.Cu → F.Cu) around (50.50, 118.80) mm near Q21: 0.632 A in total, up to 0.123 A per via, 0.31 mV across the barrels; 1.0% share of loss. Left out: S1 (measured against the default 3 % limit). Scenario B: 3 suggestions and 20 bottlenecks -------------------------------------------- - [S1, current density, Module VDD_IN path] Narrow passage in zone +5V_SoM on F.Cu (+5V_SoM, about 0.91 mm wide) near (57.21, 90.43) mm reaches 38.6 A/mm² at (57.26, 90.51) mm (averaged over 0.1 mm), above the heuristic 35 A/mm² limit. At the same current the density falls roughly in proportion to the width: about ×1.10 wider copper there meets it. The limit is a heuristic (it depends on cooling and reliability targets). (at average current, not a verdict: the current-basis gate withholds heuristic flags here) - [S2, current density, Module VDD_IN path] The current density on F.Cu (/Supply/5V_OUT + +5V + +5V_SoM + /SoM/SoM_VIN + VDD_SoM) reaches 189 A/mm² at (56.55, 88.84) mm, above the heuristic 35 A/mm² limit (averaged over 0.1 mm). Spread the current there: more copper, more or larger vias, or a larger contact. The limit is a heuristic. (at average current, not a verdict: the current-basis gate withholds heuristic flags here) - [S3, current density, GND] Trace B2 on F.Cu (GND) from U18 pad 2 (102.35, 120.55) mm to via #390 (102.05, 119.25) mm, 0.3 mm wide in 35 µm copper, carries up to 0.9 A: 85.7 A/mm² in the trace body (up to 103 A/mm² at (102.21, 119.64) mm, averaged over 0.1 mm), above the heuristic 35 A/mm² limit. A width of at least 0.735 mm (I/(J_limit×t)) brings the trace body to the limit at this current. Where the current turns or enters a pad or via the density is 1.21× the body value here, so such spots stay above the limit unless they are widened too. The limit is a heuristic (it depends on cooling and reliability targets). (at average current, not a verdict: the current-basis gate withholds heuristic flags here) - [B1, link, Module VDD_IN path] Series link U29 at (56.73, 90.05) mm: 82.0% share of loss. - [B2, link, Module VDD_IN path] Series link Q6 at (59.36, 92.05) mm: 8.2% share of loss. - [B3, link, Module VDD_IN path] Series link R172 at (55.34, 92.59) mm: 1.5% share of loss. - [B4, link, Module VDD_IN path] Series link R287 at (57.30, 87.50) mm: 0.9% share of loss. - [B5, plane region, Module VDD_IN path] zone /Supply/5V_OUT on F.Cu copper in a 2 × 2 mm area, loss centred near (53.54, 94.91) mm: 1.99 mV across the area, up to 63.8 A/mm²; 0.9% share of loss. - [B6, plane region, Module VDD_IN path] zone +5V_SoM on F.Cu copper in a 2 × 2 mm area, loss centred near (56.98, 91.70) mm: 1.45 mV across the area, up to 155 A/mm²; 0.9% share of loss. - [B7, plane region, Module VDD_IN path] zone VDD_SoM on F.Cu copper in a 2 × 2 mm area, loss centred near (56.53, 88.61) mm near R287: 1.25 mV across the area, up to 189 A/mm²; 0.7% share of loss. - [B8, plane region, Module VDD_IN path] zone /Supply/5V_OUT on F.Cu copper in a 2 × 2 mm area, loss centred near (53.54, 96.59) mm: 1.13 mV across the area, up to 92.5 A/mm²; 0.5% share of loss. - [B9, plane region, Module VDD_IN path] zone /Supply/5V_OUT on F.Cu copper in a 2 × 2 mm area, loss centred near (54.50, 94.87) mm near C103: 2.17 mV across the area, up to 106 A/mm²; 0.5% share of loss. - [B10, plane region, Module VDD_IN path] zone /Supply/5V_OUT on F.Cu copper in a 2 × 2 mm area, loss centred near (53.64, 93.34) mm: 1.29 mV across the area, up to 80.2 A/mm²; 0.4% share of loss. - [GND B1, via, GND] Via #390 (0.1 mm drill, F.Cu → In6.Cu) at (102.05, 119.25) mm: 0.9 A, 4.58 mV across the barrel; 35.3% share of loss. - [GND B2, trace, GND] Trace on F.Cu, 0.3 mm wide and 0.619 mm long (outside pads, vias and zones) from U18 pad 2 (102.35, 120.55) mm to via #390 (102.05, 119.25) mm: 0.885 mV across it at 0.9 A, up to 103 A/mm²; 6.8% share of loss. - [GND B3, via cluster, GND] Cluster of 7 vias (0.1 mm drill, In1.Cu → F.Cu) around (51.70, 119.40) mm near J12, U11: 1.64 A in total, up to 0.422 A per via, 0.507 mV across the barrels; 3.4% share of loss. - [GND B4, via cluster, GND] Cluster of 11 vias (0.1 mm drill, In4.Cu → F.Cu) around (61.68, 95.97) mm near C6, C103, C120, C129, C153: 0.99 A in total, up to 0.134 A per via, 0.492 mV across the barrels; 3.0% share of loss. - [GND B5, plane region, GND] zone GND on F.Cu copper in a 2 × 2 mm area, loss centred near (51.71, 119.04) mm near J12: 0.226 mV across the area, up to 46.6 A/mm²; 2.2% share of loss. - [GND B6, plane region, GND] zone GND on In1.Cu copper in a 10 × 9.2 mm area, loss centred near (54.49, 121.87) mm near D6, D53, J3, J12, U11: 0.306 mV across the area, up to 9.86 A/mm²; 1.3% share of loss. - [GND B7, via cluster, GND] Cluster of 7 vias (0.1 mm drill, F.Cu → In2.Cu) around (62.77, 81.80) mm near D31: 0.824 A in total, up to 0.143 A per via, 0.279 mV across the barrels; 1.2% share of loss. - [GND B8, plane region, GND] zone GND on F.Cu copper in a 2 × 0.8 mm area, loss centred near (51.59, 120.16) mm: 0.256 mV across the area, up to 47.5 A/mm²; 1.2% share of loss. - [GND B9, plane region, GND] zone GND on In6.Cu copper in a 10 × 9.2 mm area, loss centred near (102.06, 120.59) mm near C74, C75, D11, D55, J5: 0.304 mV across the area, up to 16 A/mm²; 1.1% share of loss. - [GND B10, plane region, GND] zone GND on F.Cu copper in a 2.01 × 2.01 mm area, loss centred near (61.82, 94.41) mm near C6: 0.217 mV across the area, up to 18.1 A/mm²; 1.0% share of loss. Scenario G: 6 suggestions and 20 bottlenecks -------------------------------------------- - [S2, link resistance, Module VDD_IN path] U29 (load switch, 45 mΩ (config, given)) carries 5.27 A and drops 237 mV — 92 % of SoM_VDD_IN's total drop (258 mV) … - [S3, link resistance, Module VDD_IN path] R287 (jumper, 0.5 mΩ (config, given)) carries 5.27 A and drops 2.64 mV — 1 % of SoM_VDD_IN's total drop (258 mV) … - [S4, link resistance, Module VDD_IN path] R172 (jumper, 0.5 mΩ (config, given)) carries 6.17 A and drops 3.09 mV — 1 % of SoM_VDD_IN's total drop (258 mV) … - [S5, current density, Module VDD_IN path] Narrow passage in zone +5V_SoM on F.Cu (+5V_SoM, about 0.91 mm wide) near (57.22, 90.50) mm reaches 70.4 A/mm² at (57.26, 90.51) mm (averaged over 0.1 mm), above the heuristic 35 A/mm² limit. At the same current the density falls roughly in proportion to the width: about ×2.01 wider copper there meets it. The limit is a heuristic (it depends on cooling and reliability targets). (at average current, not a verdict: the current-basis gate withholds heuristic flags here) - [S6, current density, Module VDD_IN path] The current density on F.Cu (/Supply/5V_OUT + +5V + +5V_SoM + /SoM/SoM_VIN + VDD_SoM) reaches 332 A/mm² at (56.55, 88.84) mm, above the heuristic 35 A/mm² limit (averaged over 0.1 mm). Spread the current there: more copper, more or larger vias, or a larger contact. The limit is a heuristic. (at average current, not a verdict: the current-basis gate withholds heuristic flags here) - [S7, current density, GND] Trace B4 on F.Cu (GND) from U18 pad 2 (102.35, 120.55) mm to via #390 (102.05, 119.25) mm, 0.3 mm wide in 35 µm copper, carries up to 0.9 A: 85.7 A/mm² in the trace body (up to 103 A/mm² at (102.21, 119.64) mm, averaged over 0.1 mm), above the heuristic 35 A/mm² limit. A width of at least 0.735 mm (I/(J_limit×t)) brings the trace body to the limit at this current. Where the current turns or enters a pad or via the density is 1.21× the body value here, so such spots stay above the limit unless they are widened too. The limit is a heuristic (it depends on cooling and reliability targets). (at average current, not a verdict: the current-basis gate withholds heuristic flags here) - [B1, link, Module VDD_IN path] Series link U29 at (56.73, 90.05) mm: 88.6% share of loss. - [B2, link, Module VDD_IN path] Series link Q6 at (59.36, 92.05) mm: 2.9% share of loss. - [B3, link, Module VDD_IN path] Series link R172 at (55.34, 92.59) mm: 1.3% share of loss. - [B4, link, Module VDD_IN path] Series link R287 at (57.30, 87.50) mm: 1.0% share of loss. - [B5, plane region, Module VDD_IN path] zone +5V_SoM on F.Cu copper in a 2 × 2 mm area, loss centred near (56.98, 91.70) mm: 2.34 mV across the area, up to 256 A/mm²; 0.8% share of loss. - [B6, plane region, Module VDD_IN path] zone VDD_SoM on F.Cu copper in a 2 × 2 mm area, loss centred near (56.53, 88.61) mm near R287: 2.2 mV across the area, up to 332 A/mm²; 0.8% share of loss. - [B7, plane region, Module VDD_IN path] zone /Supply/5V_OUT on F.Cu copper in a 2 × 2 mm area, loss centred near (53.54, 94.91) mm: 3.15 mV across the area, up to 101 A/mm²; 0.8% share of loss. - [B8, plane region, Module VDD_IN path] zone /Supply/5V_OUT on F.Cu copper in a 2 × 2 mm area, loss centred near (53.54, 96.59) mm: 1.78 mV across the area, up to 146 A/mm²; 0.5% share of loss. - [B9, plane region, Module VDD_IN path] zone /Supply/5V_OUT on F.Cu copper in a 2 × 2 mm area, loss centred near (54.50, 94.87) mm near C103: 3.44 mV across the area, up to 167 A/mm²; 0.4% share of loss. - [B10, plane region, Module VDD_IN path] zone /SoM/SoM_VIN on F.Cu copper in a 2 × 2 mm area, loss centred near (58.73, 85.99) mm: 2.41 mV across the area, up to 98.8 A/mm²; 0.3% share of loss. - [GND B1, via, GND] Via #390 (0.1 mm drill, F.Cu → In6.Cu) at (102.05, 119.25) mm: 0.9 A, 4.58 mV across the barrel; 22.4% share of loss. - [GND B2, via cluster, GND] Cluster of 7 vias (0.1 mm drill, In1.Cu → F.Cu) around (51.70, 119.40) mm near J12, U11: 2.38 A in total, up to 0.613 A per via, 0.737 mV across the barrels; 4.6% share of loss. - [GND B3, via cluster, GND] Cluster of 11 vias (0.1 mm drill, In4.Cu → F.Cu) around (61.68, 95.97) mm near C6, C103, C120, C129, C153: 1.53 A in total, up to 0.207 A per via, 0.757 mV across the barrels; 4.5% share of loss. - [GND B4, trace, GND] Trace on F.Cu, 0.3 mm wide and 0.619 mm long (outside pads, vias and zones) from U18 pad 2 (102.35, 120.55) mm to via #390 (102.05, 119.25) mm: 0.885 mV across it at 0.9 A, up to 103 A/mm²; 4.3% share of loss. - [GND B5, plane region, GND] zone GND on F.Cu copper in a 2 × 2 mm area, loss centred near (51.71, 119.04) mm near J12: 0.329 mV across the area, up to 67.8 A/mm²; 3.0% share of loss. - [GND B6, plane region, GND] zone GND on In1.Cu copper in a 10 × 9.2 mm area, loss centred near (54.49, 121.87) mm near D6, D53, J3, J12, U11: 0.443 mV across the area, up to 14.3 A/mm²; 1.8% share of loss. - [GND B7, via cluster, GND] Cluster of 7 vias (0.1 mm drill, F.Cu → In2.Cu) around (62.77, 81.80) mm near D31: 1.22 A in total, up to 0.213 A per via, 0.414 mV across the barrels; 1.7% share of loss. - [GND B8, plane region, GND] zone GND on F.Cu copper in a 2 × 0.8 mm area, loss centred near (51.59, 120.16) mm: 0.372 mV across the area, up to 69 A/mm²; 1.6% share of loss. - [GND B9, plane region, GND] zone GND on F.Cu copper in a 2.01 × 2.01 mm area, loss centred near (61.82, 94.41) mm near C6: 0.332 mV across the area, up to 27.8 A/mm²; 1.5% share of loss. - [GND B10, plane region, GND] zone GND on F.Cu copper in a 2.01 × 2.01 mm area, loss centred near (61.75, 91.69) mm near C5, C152, D32: 0.36 mV across the area, up to 20.8 A/mm²; 1.3% share of loss. Left out: S1 (measured against the default 3 % limit). WHAT WAS AND WAS NOT MODELLED ============================= - The scenarios and the currents are ours. The module's current is a constant current: in A and B a mode's power budget over its supply's nominal voltage (the 9.0 V input for A, the 5 V buck's 5.0 V setpoint for B), in C 40 W over the 9.0 V input, in F 25 W over the 5.0 V setpoint, in D NVIDIA's 5 A absolute-maximum VDD_IN current, and in E and G the current at which the module receives 40 W or 25 W at its computed VDD_IN. - Nothing here is measured, and pdnsim's measured accuracy is none yet. - It is a DC solution: no transients, and no losses in watts (pdnsim withholds them at an average current). No temperature either: the copper is taken at a uniform 25 °C for its resistivity only, and the parts at their stated values. - Copper: the file gives all eight copper layers KiCad's default 35 µm, and we have no fab stackup. So pdnsim computes on 35 µm and gives no verdict. A copper row scales with 1/thickness: thinner copper, larger copper rows (not run). - The parts' resistances are stated values: the P-FETs at Toshiba's maximum at 25 °C and |VGS| 4.5 V (not a bound), the eFuses at TI's maximum over −40 to 125 °C (typical 28.2 mΩ at VIN 12 V, IOUT 3 A, TJ 25 °C), the jumpers at ROHM's maximum. - Not modelled, and each would take more of the margin: the contact resistance of the input connector J12 and of the module socket J15; the module's own copper; the input cable and supply; the LDOs U41 and U42, and every small carrier load; heating of the copper and of the parts (the P-FETs' resistance rises as they heat). - Also not modelled, and they move VDD_IN either way: the 5 V buck's setpoint tolerance and load regulation. They move VDD_IN in the 5 V scenarios by as much as they move the 5.0 V. - The PoE and USB-PD inputs are other ways to power the board. They are not modelled: every scenario here is fed at J12. - NVIDIA's instantaneous limits are higher than or equal to the average powers used here (30 W for the Orin NX 16GB's 25 W mode, 20 W for the Orin Nano 8GB's 15 W mode; 25 W, equal to its average, for its 25 W* mode). The carrier loads (USB-C1 0.9 A, the NVMe SSD 1.5 A, the M.2 key E card 0.5 A) are our estimates, and the bucks' efficiencies were read by eye from Antmicro's plots (in F and G the 5 V buck's output, 5.90 A and 6.17 A, is beyond the 4 A end of the curve we read; that changes only the 9 V input's numbers, not the module's path). NUMERICAL CONVERGENCE, NOT ACCURACY =================================== pdnsim splits the copper into many small pieces (a mesh) and refines the mesh until the answer stops changing. Each figure is pdnsim's change, between its last two meshes, of the worst load's supply drop (for GND: of the largest ground rise). It checks the arithmetic, not how close the answer is to a real board. - Scenario E: Module VDD_IN path 0.026 % (119,924 nodes); Carrier 5 V 0.062 % (116,836 nodes); Carrier 3.3 V 0.348 % (160,993 nodes); GND 0.166 % (1,463,758 nodes). - Scenario A: Module VDD_IN path 0.026 % (119,924 nodes); Carrier 5 V 0.062 % (116,836 nodes); Carrier 3.3 V 0.348 % (160,993 nodes); GND 0.164 % (1,463,758 nodes). - Scenario B: Module VDD_IN path 0.035 % (136,492 nodes); 9 V input 0.039 % (98,197 nodes); Carrier 3.3 V 0.348 % (160,993 nodes); GND 0.182 % (1,463,758 nodes). - Scenario G: Module VDD_IN path 0.033 % (136,492 nodes); 9 V input 0.040 % (98,197 nodes); Carrier 3.3 V 0.348 % (160,993 nodes); GND 0.195 % (1,463,758 nodes). SOURCES ======= - Antmicro, Jetson Orin Baseboard, KiCad design at commit 34f0e7f (Apache-2.0): https://github.com/antmicro/jetson-orin-baseboard/tree/34f0e7f5fbca441191e20ed55d93cf8614e12bed - Antmicro, doc/source/getting_started.md at 34f0e7f: https://github.com/antmicro/jetson-orin-baseboard/blob/34f0e7f5fbca441191e20ed55d93cf8614e12bed/doc/source/getting_started.md - Antmicro, doc/source/board_overview.md at 34f0e7f: https://github.com/antmicro/jetson-orin-baseboard/blob/34f0e7f5fbca441191e20ed55d93cf8614e12bed/doc/source/board_overview.md - Antmicro, doc/source/img/5V_eff_temp_vs_output_curr.png at 34f0e7f (5 V buck efficiency and output voltage plots): https://github.com/antmicro/jetson-orin-baseboard/blob/34f0e7f5fbca441191e20ed55d93cf8614e12bed/doc/source/img/5V_eff_temp_vs_output_curr.png - Antmicro, doc/source/img/3V3_eff_temp_vs_output_curr.png at 34f0e7f (3.3 V buck efficiency and output voltage plots): https://github.com/antmicro/jetson-orin-baseboard/blob/34f0e7f5fbca441191e20ed55d93cf8614e12bed/doc/source/img/3V3_eff_temp_vs_output_curr.png - NVIDIA, Jetson Orin NX Series Modules Data Sheet, DS-10712-001_v1.7 (February 2026): https://developer.nvidia.com/downloads/jetson-orin-nx-module-series-data-sheet - NVIDIA, Jetson Linux Developer Guide r36.4, Platform Power and Performance, "Software-Based Power Consumption Modeling": https://docs.nvidia.com/jetson/archives/r36.4/DeveloperGuide/SD/PlatformPowerAndPerformance/JetsonOrinNanoSeriesJetsonOrinNxSeriesAndJetsonAgxOrinSeries.html - NVIDIA developer forum, "How to handle MODULE_ID (Pin 217)", moderator reply of 2024-07-04 (a forum post, not a data sheet): https://forums.developer.nvidia.com/t/how-to-handle-module-id-pin-217/298485 (SHA-256 of the copy we read: 95cd540495a7c38c4fc33a3f40c253512c5e24b5660571f513f89ab346f53ad4) - Texas Instruments, TPS25947xx data sheet SLVSFC9C: https://www.ti.com/lit/ds/symlink/tps25947.pdf - Toshiba, SSM3J332R data sheet (2018-10-15), a copy hosted by Farnell (Toshiba's own copy refused our download): https://www.farnell.com/datasheets/3622419.pdf (SHA-256 of the copy we read: fedd3bc3daeedcec6297ee272bda6e57870b2d619e8b9e8bf110ea3bc94cacd7) - ROHM, PMR series jumper type data sheet (copy hosted by LCSC): https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/1810162127_ROHM-Semicon-PMR03EZPJ000_C253507.pdf Board: Jetson Orin Baseboard by Antmicro, Copyright (c) 2022-2026 Antmicro, licensed Apache-2.0 (https://github.com/antmicro/jetson-orin-baseboard/blob/34f0e7f5fbca441191e20ed55d93cf8614e12bed/LICENSE). Its published file is analysed unmodified; the scenarios are ours, and no endorsement by Antmicro or NVIDIA is implied.